As the fabrication technology of semiconductor devices advances, semiconductor devices are having higher device density and higher level of integration. Being a basic type of semiconductor device, transistors are widely used. Higher device density and higher level of integration causes gate electrodes of planar transistors to have smaller dimensions. As a result, traditional planar transistors have weaker control of channel current, and the short channel effect often occurs. Thus, leakage current can be generated, and the electrical properties of the semiconductor devices are adversely affected.
Currently, to overcome the short channel effect and to suppress leakage current, fin field effect transistors (FinFETs) are used. As a common multi-gated device, a FinFET often includes a fin and a dielectric layer on the semiconductor substrate. The dielectric layer covers a portion of a sidewall of a fin. The surface of the dielectric layer is lower than the top surface of the fin. The FinFET also includes a gate structure. The gate structure is often disposed on the dielectric layer and the top surface and the sidewalls of the fin. The FinFET also includes a source and drain region, located in the fin on the two sides of the gate structure.
The source and the drain region, located in the fins on the two sides of a gate structure, is referred as a raised source and drain region. As the dimensions of the semiconductor devices shrink, it is becoming more difficult to form the raised source and drain region in a FinFET. In addition, a source and drain region formed in a stress layer often has impaired properties.
The disclosed semiconductor device and fabrication method are directed to solve one or more problems set forth above and other problems.